Electronic component for amplifying high frequency and radio communication system

ABSTRACT

A high-frequency power module as a component of a radio communication system capable of performing communications in two frequency bands such as GSM and DCS and has a first transistor for output detection for receiving a signal which is the same as an input signal of a first power amplification transistor for amplifying a high frequency signal on the GSM side and a first current mirror circuit for passing current proportional to current of the transistor. A second transistor for output detection for receiving an input signal of a second power amplification transistor for amplifying a high frequency signal on the DCS side is also provided as is a second current mirror circuit for passing current proportional to current of the transistor. Conversion of current transferred from the first and second current mirror circuits to voltage is shared by the GSM and DCS.

INCORPORATION BY REFERENCE

The present application claims priority from PCT applicationPCT/JP02/009053 filed on Sep. 5, 2002, the content of which is herebyincorporated by reference into this application.

TECHNICAL FIELD

The present invention relates to a technique effective when applied to ahigh-frequency power amplifying circuit for amplifying a high frequencysignal and outputting the amplified signal and to a radio communicationsystem such as a portable telephone in which the high-frequency poweramplifying circuit is assembled. More particularly, the inventionrelates to a technique enabling the number of parts to be reduced bymaking elements of a circuit for detecting an output level necessary foran output power feedback control commonly used in a radio communicationsystem having a plurality of high-frequency power amplifying circuits inaccordance with transmission frequency bands.

BACKGR0UND ART

Hitherto, there is a system called a GSM (Global System for MobileCommunication) using frequencies in a band of 880 to 915 MHz which isemployed in Europe as one of systems of radio communication apparatuses(mobile communication apparatuses) such as mobile telephones. In theGSM, as a modulation system, a phase modulation system called GMSK(Gaussian Minimum Shift Keying) for shifting the phase of a carrier wavein accordance with transmission data is used.

Generally, a high-frequency power amplifying circuit for amplifying amodulated signal is assembled in a transmission-side output part in aradio communication apparatus. In a conventional GSM radio communicationapparatus, to control the amplification factor of the high-frequencypower amplifying circuit in accordance with a transmission request levelfrom a control circuit such as a baseband circuit or a microprocessor,an output level of the high-frequency power amplifying circuit or anantenna is detected and fed back (for example, Japanese Patent Laid-openNo. 2000-151310). Conventionally, the output level is generally detectedby using a coupler, a detector, or the like, and the detector is oftenconstructed as a semiconductor integrated circuit separate from thehigh-frequency power amplifying circuit.

The coupler is a device for detecting an output level via a capacitanceformed between an output line (microstrip line) formed in a discretepart or an insulating substrate (module substrate) and a conductordisposed in parallel with the output line. The size of the coupler islarger than that of a device formed on a semiconductor chip. Adirectional coupler is described in, for example, “Basics andApplication of Microwaves” issued on Jul. 10, 1997, Sogo ElectronicsPress, pp. 191 to 193. “Electronic Materials” issued in April, 1999 byKogyo Chosakai Publishing Co., Ltd. pp. 91 to 95 describes a ceramicstacked-layer low-pass filter for mobile communication and a directionalcoupler.

Since the system of detecting the output level of the conventionalhigh-frequency power amplifying circuit uses a number of semiconductorintegrated circuits and electronic parts separate from thehigh-frequency power amplifying circuit, it is difficult to reduce thesize of the module. In the case of using also a coupler, a referencevoltage may be applied to one end of the coupler to improve detectionsensitivity. In this case, optimum setting of the reference voltage andadjustment of a voltage according to variations in parts are necessary.Consequently, there is an inconvenience such that the burden on a setupmaker increases. When the coupler is used, there is an inconveniencesuch that power loss also occurs.

Further, as a portable telephone of recent years, a dual-band portabletelephone capable of handling not only a signal of the GSM but also asignal of a system such as a DCS (Digital Cellular System) usingfrequencies of, for example, 1710 to 1785 MHz is proposed. In ahigh-frequency power amplifying module used in such a portabletelephone, an output power amplifier is provided for each of the bandsand a coupler for detecting the output level of the module is alsonecessary for each of the bands. Consequently, it is difficult to reducethe size of the module.

An object of the invention is to provide an electronic component(module) for amplifying high-frequency power, realizing a reducedcircuit scale and a reduced power loss in the case of detecting anoutput level in a radio communication system capable of performingcommunications in two frequencybands such as GSM and DCS, comparing thedetected output level with a required output level, and controlling theamplification factor ofa high-frequency power amplifying circuit foramplifying an input signal.

Another object of the invention is to provide an electronic componentfor amplifying high-frequency power, capable of detecting an outputlevel necessary for feedback control in a current detecting method in aradio communication system capable of performing communications in twofrequency bands such as GSM and DCS, so that it is unnecessary to adjusta voltage and the like and the load on a setup maker can be lessened.

Further, another object of the invention is to provide an electroniccomponent for amplifying high-frequency power in a radio communicationsystem capable of performing communications in two frequency bands suchas GSM and DCS, in which leakage of a signal from a high-frequency poweramplifying circuit in an idle state can be prevented at the time oftransmission of the other high-frequency power amplifying circuit, andto a radio communication system using the same.

The above and other objects and novel features of the invention willbecome apparent from the description of the specification and attacheddrawings.

DISCLOSURE OF THE INVENTION

The outline of representative ones of inventions disclosed in thespecification will be briefly described as follows.

According to the invention, an electronic component for amplifying ahigh-frequency power (RF power module) as a component of a radiocommunication system capable of performing communications in twofrequency bands such as GSM and DCS includes: a first output detectiontransistor for receiving a signal which is the same as an input signalof a first power amplification transistor for amplifying a highfrequency signal on the GSM side and a first current mirror circuit forpassing current proportional to current of the transistor; and a secondtransistor for output detection for receiving an input signal of asecond power amplification transistor for amplifying a high frequencysignal on the DCS side and a second current mirror circuit for passingcurrent proportional to current of the transistor. A sense resistor forconverting current on the transfer side of the current mirror circuitsto voltage, using the voltage as an output level detection signal,comparing the detected output level with a required output level,accordingly controlling the output level, and converting currenttransferred from the first and second current mirror circuits to voltageand, more preferably, a comparing circuit for comparing the detectedoutput level with the requested output level are shared by the GSM andDCS.

When the output level of a high frequency signal in a first frequencyband such as GSM and that of a high frequency signal in a secondfrequency band such as DCS are different from each other, each of thesize ratio between the power amplification transistor in the final stageof a high-frequency power amplification circuit and the transistor foroutput detection and the size ratio between the transistors in thecurrent mirror circuits is set so that magnitudes of currents flowing inthe sense resistor become almost equal to each other in the case whereeither a first or second high-frequency power amplifying circuitoperates at a maximum output level. With the configuration, the outputlevel necessary for a feedback control can be detected by a currentdetecting method, so that power loss can be decreased. It is unnecessaryto adjust a voltage and the like, so that the load on a setup maker canbe lessened. Moreover, by sharing the sense resistor and the comparingcircuit, the number of parts constructing the high-frequency amplifyingcircuit is decreased and the size of the radio communication system canbe reduced.

Preferably, the electronic component for amplifying high-frequency powerincludes: a first amplifying circuit in which a plurality of poweramplification transistors for amplifying a modulated high-frequencysignal in a first frequency band are cascaded; and a second amplifyingcircuit in which a plurality of power amplification transistors foramplifying a modulated high-frequency signal in a second frequency bandare cascaded. The first transistor for output detection and the secondtransistor for output detection are constructed so as to receive inputsignals of the power amplification transistors in the final stage of thefirst and second amplifying circuits. By constructing the poweramplifying circuit by a plurality of amplification stages, for example,a control for applying a bias by which the gain in the firstamplification stage is suppressed and the gain in the post amplificationstages increases can be performed. Thus, it becomes easier to obtaindesired characteristics as a whole, and an output level necessary for afeedback control can be detected by the current detecting method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the configuration of aradio communication system using an electronic component for amplifyinghigh-frequency power (hereinbelow, called an RF power module) accordingto the invention.

FIG. 2 is a circuit diagram showing an example of the RF power moduleaccording to the invention.

FIG. 3 is a current waveform diagram showing change with time of currentflowing in the final stage in a high-frequency power amplifying circuitin the case where output power is high and that in the case where outputpower is low.

FIG. 4 is a circuit diagram showing a concrete example of ahigh-frequency power amplifying circuit and an output detection circuitin the RF power module of the embodiment.

FIG. 5 is a circuit diagram showing another configuration example of theoutput detection circuit.

FIG. 6 is a graph showing the relation between output power Pout in theRF power module in the embodiment and detection current ISNS of theoutput detection circuit.

FIG. 7 is a circuit diagram showing a second embodiment of the RF powermodule.

FIG. 8 is a circuit diagram showing a third embodiment of the RF powermodule.

FIG. 9 is a circuit configuration diagram showing a concrete example ofa front end module provided in the post stage of the RF power module ofthe embodiment.

FIG. 10 is a partially-sectional perspective view schematically showingthe device structure of the RF power module of the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the invention will be described in detail hereinbelowwith reference to the drawings.

FIG. 1 shows a schematic configuration of a system capable of performingradio communications of two communication systems of GSM and DCS towhich the invention is applied.

In FIG. 1, 100 denotes a high-frequency module (hereinbelow, called RFmodule) obtained by mounting a high-frequency signal processing circuit(RF IC) 110 formed as a semiconductor integrated circuit having amodulating/demodulating circuit capable of performing GMSK modulationand demodulation in the systems of GSM and DCS, band pass filters SAWtaking the form of surface acoustic wave filters for removingunnecessary waves from a reception signal, low-noise amplifiers LNA foramplifying a reception signal, and the like on a ceramic substrate. 200denotes an RF power module including high-frequency power amplifyingcircuits (hereinbelow, called power amplifiers) PA for transmitting asignal by driving the antenna ANT and an output power control circuit230. 300 denotes a baseband circuit (hereinbelow, called a baseband IC)formed as a semiconductor integrated circuit for generating I and Qsignals on the basis of transmission data (baseband signal) andprocessing I and Q signals extracted from a reception signal. 400indicates a front end module including filters LPF for removing noisesuch as harmonics included in a transmission signal output from thepower module 200, transmission/reception change-over switches, and abranching filter. 500 indicates a microprocessor (hereinbelow, called aCPU) for controlling the whole system by generating control signals tothe RF IC 110 and the baseband IC 300 and generating an output levelinstruction signal Vramp to the RF power module 200.

As shown in FIG. 1, in the embodiment, the RF power module 200 hastherein a power amplifier 210 a for amplifying a transmission signal of900 MHz in the frequency band of the GSM and a power amplifier 210 b foramplifying a transmission signal of 1800 MHz in the frequency band ofthe DCS. Similarly, the RF module 100 has therein an SAW filter 120 aand a low noise amplifier 130 a for the GSM and an SAW filter 120 b anda low noise amplifier 130 b for the DCS.

In the RF IC 110, GMSK modulation of phase-modulating a carrier wave inaccordance with desired information to be transmitted is performed, andthe phase-modulated signal is input as a high frequency signal Pin tothe RF power module 200 and amplified. Although not limited, in theembodiment, the RF IC 110 includes not only the modulating circuit fortransmission but also a reception circuit constructed by a mixer fordown-converting a reception signal to a signal of a lower frequency, aprogrammable gain amplifier of a high gain, and the like. The low noiseamplifier LNA can be also provided in the RF IC 110.

The front end module 400 includes a low pass filter 410 a for GSM, a lowpass filter 410 b for DCS, a change-over switch 420 a for switchingtransmission/reception of the GSM, a change-over switch 420 b forswitching transmission/reception of the DCS, and a branching filter 430which is connected to the antenna ANT and separates a signal for GSM anda signal for DCS from a reception signal. Although not shown in FIG. 1,the RF power module 200 or front end module 400 is provided withimpedance matching circuits connected between the output terminals ofthe power amplifiers 210 a and 210 b or transmission output terminals ofthe RF power module 200 and the low pass filters 410 a and 410 b andperforming impedance matching.

FIG. 2 shows a schematic configuration of a first embodiment of the RFpower module 200 to which the invention is applied.

The RF power module 200 of the embodiment has: an output detectioncircuit 220 including amplifiers 221 a and 221 b for detecting outputcurrents of the power amplifiers 210 a and 210 b, current mirrorcircuits 222 a and 222 b for generating current proportional to thecurrent of the amplifiers, and a sense resistor Rs for convertingcurrent on a transfer side of the current mirror circuits to voltage;and the output power control circuit 230 for comparing a detectionsignal of the output detection circuit 220 with the output levelinstruction signal Vramp from the CPU 500 and controlling the poweramplifiers 210 so that the output power of the power amplifiers 210 aand 210 b becomes a level according to the output level instructionsignal Vramp.

The instruction level of the output level instruction signal Vramp isset to be low when it is near a base station as a communication partyand is set to be high when it is far from the base station. The outputlevel instruction signal Vramp may be generated in the RF IC 110 inresponse to an instruction from the CPU 500. The CPU 500 outputs notonly the output level instruction signal Vramp but also a transmissionstart signal TXON to the RF power module 200. The transmission startsignal TXON may be supplied to the RF power module 200 from the basebandLSI 300 or RF IC 110.

As shown in FIG. 2, in the embodiment, the sense resistor Rs is sharedby a circuit for detecting output current of the power amplifier 210 aon the GSM side and a circuit for detecting output current of the poweramplifier 210 b on the DCS side. Since the maximum level of the outputpower of the power amplifier 210 a on the GSM side and that of theoutput power of the power amplifier 210 b on the DCS side are specifiedaccording to standards and different from each other, the sense resistorRs cannot be shared simply. In the embodiment, by the following devices,sharing of the sense resistor Rs is realized.

Since the sense resistor Rs has to be highly precise, it is mounted as adiscrete part on the module. By sharing the sense resistor Rs by the GSMside and the DCS side as described above, the number of parts isdecreased and the size of the module can be reduced. By mounting thesense resistor Rs as a discrete part on the module, the sense resistorRs having a desired resistance value can be selected according to thecharacteristics of the power amplifiers 210 a and 210 b and mounted.

The output power control circuit 230 includes: a comparing circuit 231for comparing a detection signal of the output detection circuit 220with the output level instruction signal Vramp and generating an outputcontrol voltage Vacp according to the difference between the signals;and a bias control circuit 232 for generating and supplying biascurrents Ic1, Ic2, and Ic3 to the power amplifiers 210 a and 210 b inaccordance with the output control voltage Vapc output from thecomparing circuit 231, a mode signal “Mode” supplied from the CPU 500and indicative of the GSM mode of transmitting a signal in accordancewith the GSM or the DCS mode of transmitting a signal in accordance withthe DCS, and the like. When the circuit for detecting the output currentof the power amplifier 210 a on the GSM side and the circuit fordetecting the output current of the power amplifier 210 b on the DCSside share the sense resistor Rs, by adjusting current passed to thesense resistor Rs, the comparing circuit 231 can be also shared.

In the CPU 500 or baseband LSI 300, the characteristics of the RF IC 100and RF power module 200 are obtained in advance, data in a table formatindicative of the relation between the output level instruction signalVramp necessary to output a desired output level signal from the RFpower module 200 and a required output level is generated and stored inan internal nonvolatile memory or the like, and the output levelinstruction signal Vramp according to the required output level obtainedby transmission/reception to/from a base station is generated withreference to the table and is output. When the RF IC 100 has acorrection circuit for correcting variations in characteristics,correction data may be stored in a nonvolatile memory in the CPU 500 orbaseband LSI 300.

FIG. 4 shows a concrete circuit example of the RF power module 200 inthe embodiment. In FIG. 4, only the power amplifier 210 a and an outputdetection circuit 220 a on the GSM side are shown, and the poweramplifier 210 b and an output detection circuit 220 b on the DCS sideare not shown. Although not particularly limited, in the embodiment, theoutput power control circuit 230 for controlling the bias currents Ic1,Ic2, and Ic3 passed to the amplification stages of the power amplifier210 a is constructed as a circuit common for the GMS and DCS.

In the power amplifier 210 of the embodiment, three amplification stages211, 212, and 213 are cascaded via impedance matching circuits MN1 toMN3 for blocking direct current and performing impedance matching. Foreach of the amplification stages, a field effect transistor(hereinbelow, described as FET) for power amplification is provided.FIG. 4 shows a concrete circuit configuration of the final amplificationstage 213 and an impedance matching circuit MN4 at the post stage of theamplification stage 213. Although not shown, the first and secondamplification stages 211 and 213 have a configuration similar to that ofthe final amplification stage 213. MS7 and MS8 denote microstrip linesfunctioning as inductance elements for matching impedances formed on theceramic substrate.

The final amplification stage 213 is constructed by an FET 31 for poweramplification whose gate terminal receives an output of theamplification stage 212 as the ante-stage via the impedance matchingcircuit MN3, and an FET 32 which is connected to the FET 31 to form acurrent mirror. A power source voltage Vdd is applied to the drainterminal of the FET 31 via an inductance element L3. By passing thecontrol current Ic3 supplied from the bias control circuit 232 to thecurrent mirror FET 32, drain current Id which is the same as the controlcurrent Ic3 or proportional to the control current Ic3 is passed to theFET 31. In such a manner, currents are passed in the first and secondamplification stages 211 and 212.

By controlling the amplification factors of the amplification stages bythe control currents Ic1, Ic2, and Ic3 of the amplification stages 211to 213 by the bias control circuit 232, a signal Pout obtained byeliminating the direct current component in a high frequency inputsignal Pin and amplifying the alternate current component to a desiredlevel is output from an output terminal OUT. In the embodiment, thecontrol currents Ic1, Ic2, and Ic3 are controlled in accordance with anoutput of the comparing circuit 231 which compares the output leveldetected by the output detection circuit 220 with the output leveldesignation signal Vramp.

The bias control circuit 232 starts operating in response to the startcontrol signal TXON supplied from the CPU 500 (or baseband LSI 300) andgenerates the control currents Ic1, Ic2, and Ic3 in the GSM mode orcontrol currents Ic1′, Ic2′, and Ic3′ (Ic1′<Ic1, Ic2′<Ic2, and Ic3′<Ic3)to be supplied to the power amplifier 210 b for DCS (not shown) in theDCS mode in accordance with the mode instruction signal Mode indicativeof the GSM mode or DCS mode supplied from the CPU 500 (or baseband LSI300) in order to bias the FETs 211, 212, and 213 in the stages.

The output detection circuit 220 is constructed by an N-channel MOSFET221 having a gate terminal to which a voltage same as the gate voltageof the FET 31 for power amplification in the final stage 213 is applied,a P-channel MOSFET 222 connected to the MOSFET 221 in series between theMOSFET 221 anda power source voltage terminal Vdd0, a MOSFET 223provided in parallel with the MOFET 222, and the sense resistor Rs forconverting current to voltage, which is connected in series to theMOSFET 223.

The gate and drain of the MOSFET 222 are connected to each other and thegates of the MOSFETs 223 and 222 are commonly connected, therebyconstructing a current mirror circuit. To suppress the current flowingin the output detection circuit 220, the MOSFET 221 for output detectionwhich is smaller than the power amplification FET 31 is used. Byapplying a voltage same as the gate voltage of the power amplificationFET 31 in the final stage to the gate. terminal of the MOSFET 221,current proportional to the drain current of the FET 31 is passed to theMOSFET 221. The current is transferred by the current mirror circuit tothe resistor Rs.

Therefore, a voltage VSNS of a connection node between the resistor Rsand the MOSFET 223 becomes a voltage proportional to the current of thepower amplification FET 31 in the final stage. In the embodiment, thevoltage VSNS is fed back as an output level detection signal to thecomparing circuit 231 of the output power control circuit 230. Thecomparing circuit 231 compares the detection voltage VSNS with theoutput level designation signal Vramp from the CPU 500 and generates anoutput control voltage Vapc to the bias control circuit 232. The biascontrol circuit 232 generates the control currents Ic1, Ic2, and Ic3supplied to the power amplifier 210 a in accordance with the outputcontrol voltage Vapc.

Since the output detection circuit 220 of the embodiment is providedwith the current mirror circuit, one output terminal for outputdetection is sufficient. Specifically, although the output detectioncircuit can be constructed only by the MOSFET 221 for output detectionhaving the gate terminal to which a voltage same as the gate voltage ofthe power amplification FET 31 in the final stage is applied via aresistor Ri and the resistor (Rs) for current-voltage conversionconnected to the MOSFET 221 in series, two terminals for outputting thevoltage across both ends of the resistor for current-voltage to theoutside are necessary. In contrast, by providing the current mirrorcircuit (222 and 223) and the resistor Rs for current-voltage conversionas in the embodiment and connecting one of the terminals of the resistorRs to the ground, it becomes sufficient to use only one externalterminal for output detection.

Further, in the embodiment, the size ratio between the poweramplification FET 31 in the final stage of the power amplifiers 210 aand 210 b and the MOSFET 221 for output detection in the outputdetection circuit 220 and the size ratio between the current mirrorMOSFETs 222 and 223 of the output detection circuit 220 are set as inthe following table 1. The size ratio of FETs in the GSM and that in theDCS are different from each other for the reason that the maximum outputlevel of the output terminal of the RF power module in the GSM is set as34 dBm and that in the DCS is set as 32 dBm on the basis of maximumoutput levels at the antenna end determined in the GSM and DCSstandards. TABLE 1 GSM DCS maximum output level 34 dBm 32 dBm of RFpower module size ratio between 683:1 293:1 power FET and sense FET sizeratio of MOSFETs 6:1 7.5:1 in current mirror drain current ISNS of 10 mA12.5 mA FET for output detection current flowing in 1.67 mA 1.67 mAsense resistor Rs output power 2 W 1 W

By setting the size ratio of the FETs as described above, the senseresistor Rs and the comparing circuit 231 can be shared by the GSM andDCS. There may be also a method of applying the gate input voltage ofthe power amplification FET 31 to the gate terminal of the MOSFET 221for output detection in the output detection circuit 220 via theresistor and detecting the voltage as a DC level. However, by directlyapplying the voltage without using the resistor, an AC input can beobtained. In this manner, the correlation between the drain current Idof the power amplification FET 31 and the detection current ISNS can bemade better.

Concretely, at a low output level, the gain of the power amplificationFET 31 is small, so that the drain current Id does not become saturatedas shown by the broken line in FIG. 3. However, at a high output level,the gain of the FET 31 increases, so that the drain current Id becomessaturated as shown by the solid line in FIG. 3. On the other hand, whenan input impedance of the output detection circuit 220 is high, an inputsignal is not easily transmitted, and the amplitude of the detectioncurrent ISNS is smaller than that of the drain current Id. Even in astate where the current Id becomes saturated, the detection current ISNSof the output detection circuit 220 does not become saturated, so thatthere is no correlation between the output current Iout and thedetection current ISNS.

However, by applying the gate input of the power amplification FET 31directly to the gate terminal of the MOSFET 221 for output detection,the input impedance for the high frequency signal becomes low, and aninput signal is easily transmitted to the gate of the FET 221. When theFET 213 performs saturating operation, the FET 221 for output detectionalso performs saturating operation. Consequently, there is a correlationbetween the drain current Id of the FET 32 and the detection currentISNS and the output level can be detected at higher precision.

FIG. 5 shows another embodiment of the output detection circuit 220.

In the output detection circuit 220 of the embodiment, a resistor R4 forimproving linearity is connected between the drain terminal of the FET221 for output detection and the drain terminal of the MOSFET 222 as acomponent of the current mirror circuit. By the resistor R4, the powersource voltage dependency of the output detection circuit 220 can bereduced. The correlation between the output power Pout and the detectioncurrent ISNS in the case where the resistor R4 for improving linearityis not provided is almost linear as shown by the solid line in FIG. 6when the power source voltage Vdd0 is at a predetermined level such as3.5V. When the power source voltage Vdd0 changes to a level such as4.2V, however, current flowing in the FET 221 sharply increases in aregion in which the output power is high as shown by the broken line inFIG. 6.

On the other hand, when the resistor R4 is provided, even if the powersource voltage Vdd0 changes, the fluctuation amount of the drain voltageof the FET 221 is small. As a result, fluctuations in the currentflowing in the FET 221 can be reduced. An example of the resistancevalue of the resistor R4 for improving linearity is about 100Ω. Theresistor R4 for improving linearity on the GSM side may be set to avalue slightly larger than the resistor R4 for improving linearity onthe DCS side.

Although not particularly limited, in the embodiment, the FET in each ofthe first and second amplification stages 211 and 212 (for both of theGSM and DCS) among the components constructing the RF power module 200,a MOSFET forming a current mirror circuit in cooperation with the FET,and the MOSFETs 222 and 223 constructing the current mirror circuit ofthe output power control circuit 230 and the output detection circuit220 are formed as a semiconductor integrated circuit IC1 on a singlesemiconductor chip. The current mirror MOSFETs of the amplificationstages 211 and 212 have the same conduction type (n-channel type) asthat of the power amplification FETs and the same structure and,accordingly, have the same temperature characteristics. The fluctuationsin characteristics of the power amplifier 210 accompanying fluctuationsin temperature can be suppressed.

On the other hand, the FETs 31 (for both of the GSM and DCS) in thefinal stage 213 of the power amplifier 210, the MOSFETs 32 formingcurrent mirror circuits in cooperation with the FETs 31, and the MOSFET221 for output detection are formed as a semiconductor integratedcircuit IC2 on another semiconductor chip. As the current-voltageconverting resistor Rs and the resistor R4 for improving linearity ofthe output detection circuit 220, capacitative elements C9 to C11 in theimpedance matching circuits MN1 to MN4, and inductance element L3, andthe like, discrete parts are used.

The two semiconductor chips IC1 and IC2 and the elements such as theresistor Rs and capacitors C9 to C11 as discrete parts are mounted on acommon ceramic substrate, thereby constructing a single electroniccomponent (module) for radio communication. The microstrip lines MS7 andMS8 and the like are formed in a conductive layer pattern made of copperor the like on the ceramic substrate so as to have a desired inductancevalue. The semiconductor integrated circuit having the FET 31 in thefinal stage, the MOSFET 32 connected to the FET 31 so as to form acurrent mirror circuit, and the MOSFET 221 as a component of the outputdetection circuit 220 may be formed separately as a chip for GSM and achip for DCS.

FIG. 10 shows the device structure of the RF power module of theembodiment. FIG. 10 does not accurately show the structure of the RFpower module of the embodiment but is a structure diagram schematicallyshowing the structure while omitting some parts, wirings, and the like.

As shown in FIG. 10, body 10 of the module of the embodiment has astructure in which a plurality of dielectric films 11 taking the form ofceramic films made of alumina or the like are stacked and integrated. Onthe surface or rear face of each of the dielectric films 11, aconductive layer 12 formed in a predetermined pattern and made of asurface-plated conductor such as copper is provided. 12 a denotes awiring pattern formed by the conductive layer 12. To connect theconductive layers 12 or wiring patterns on the surface and rear face ofeach dielectric film 11, a hole 13 called a through hole is formed andfilled with a conductor.

In the module of the embodiment of FIG. 10, six dielectric films 11 arestacked. The conductive layer 12 is formed on the almost whole rear faceof each of the first, third, and sixth layers, thereby obtaining aground layer to which the ground potential GND is applied. Theconductive layers 12 on the surface and rear face of each of theremaining dielectric films 11 are used for constructing transmissionlines and the like. By properly setting the width of the conductivelayer 11 and the thickness of the dielectric film 11, the transmissionline is formed so that the impedance becomes 50 Ω.

In each of the first to third dielectric films 11, rectangular holes areformed to mount the semiconductor chips IC1 and IC2. Each of the ICs isinserted in the hole and fixed to the bottom of the hole by a jointingmaterial 14. In the fourth dielectric film 11 corresponding to thebottom of the hole and the dielectric films 11 lower than the fourthdielectric film 11, holes 15 called via holes are formed and filled witha conductor. The conductor in the via holes plays the role oftransmitting heat generated in the chips IC1 and IC2 to the lowestconductive layer to improve the discharging effect.

Electrodes on the top face of the chips IC1 and IC2 and a predeterminedconductive layer 12 are electrically connected to each other via bondingwires 31. The conductive pattern 12 a constructing the microstrip linesMS7 and MS8 and the like is formed on the surface of the firstdielectric film 11, and a plurality of discrete parts 32 such ascapacitative elements C9 to C11 and resistive elements Rs and R4 forforming the power amplifier 210, the output detection circuit 220, andthe like are mounted. The capacitative elements out of the elements canbe also formed on the inside of the substrate by using the conductivelayers on the surface and rear face of the dielectric film 11 withoutusing the discrete parts.

FIG. 7 shows a schematic configuration of a second embodiment of the RFpower module 200 to which the invention is applied.

In the RF power module 200 of the embodiment, an output terminalPout-DCS of the power amplifier 210 b on the DCS side is provided with astate switching circuit 240 including a resistor R0 connected betweenthe output terminal Pout-DCS and the power source voltage terminal Vdd,a diode D0 and a capacitor C0 connected in series between the outputterminal Pout-DCS and a reference potential point such as a groundpotential, and a resistor R1 and a switch transistor Q1 connectedbetween a connection node N0 of the diode D0 and the capacitor C0 andthe ground point. The diode D0 is preferably a PIN diode. The value ofthe capacitative element C0 may be on the order of a few pF. Theresistors R0 and R1 on the order of a few kΩ are used. By forming thetransistor Q1 on the semiconductor chip IC1 or IC2, increase in thenumber of parts can be suppressed.

The transistor Q1 is turned on in the GSM mode or turned off in the DCSmode in accordance with a control signal from the bias control circuit232. In the DCS mode in which the transistor Q1 is turned off, a currentpath formed by the resistor R0, diode D0, resistor R1, and transistor Qlis interrupted, so that the impedance of the diode D0 seen from a linethrough which a transmission signal is transmitted is high. The resistorR0 has resistance on the order of a few kΩ whereas the resistance of thetransmission line is 50Ω and the impedance is sufficiently high, so thatthe impedance ahead of the resistor R0 is not seen from the transmissionline. Therefore, at this time, the power amplifier 210 b operates in amanner similar to a circuit to which the state switching circuit 240 isnot connected.

On the other hand, in the GSM mode in which the transistor Q1 is turnedon, current flows in the path formed by the resistor R0, diode D0,resistor R1, and transistor Q1, and the potential of the output terminalof the power amplifier 210 b is fixed. It can prevent that harmonics oftwice as high as the GSM signal are transmitted to the power amplifier210 b and leaked to an output of the power amplifier 210 a on the GSMside via a filter circuit in the post stage connected to the outputterminal Pout-DCS and become noise in a transmission signal of the GSMtransmitted from the antenna.

In the DCS mode in which the transistor Q1 is turned off, the diode D0acts as a detection element and the node N1 on the cathode side of thediode D0 is fixed to a relatively high potential corresponding to themaximum amplitude level by a signal from the power amplifier 210 b.Therefore, in the embodiment, by using an MOSFET of a high-withstandvoltage as the transistor Q1, when the transistor Q1 is turned off andthe potential at the node becomes high, the transistor Q1 can beprevented from being destroyed and leak current can be prevented frombeing passed to the transistor Q1. As the MOSFET of a high-withstandvoltage, a known high-withstand-voltage element such as an LD (LaterallyDiffused) MOS can be used.

The reason why a signal output from the power amplifier 210 b on the DCSside is added to a transmission signal of the GSM in the GSM mode willbe described with reference to FIG. 9.

FIG. 9 shows a concrete circuit configuration example of one oftransmission parts (for example, DCS) in the front end module 400connected at the post stage of the RF power module 200.

In FIG. 9, the FET 31 is a transistor in the final stage of the RF powermodule 200, a transmission signal is input to the gate terminal of theFET 31, the power source voltage Vd is applied to the drain terminal viaa λ/4 transmission line TLO having an electric length of ¼ wavelength ofa fundamental wave, an impedance matching circuit 421 is connected tothe connection node between the λ/4 transmission line TLO and the drainterminal of the FET 31 and, at the post stage, a low pass filter 431, atransmission/reception switching circuit 441, and a branching filter 460for branching a GSM reception signal and a DCS reception signal aresequentially connected.

Although not limited, in the embodiment, the impedance matching circuit421 has a parallel resonance circuit PR constructed by an inductanceelement and a capacitative element, a matching means IM constructed by atransmission line and a capacitative element, and a capacitative elementDC for eliminating direct current noise from the low pass filter 431side to the power amplifier side. The constant of the circuit is set sothat the impedance of the output node of the impedance matching circuit421 becomes 50Ω. The transmission/reception switching circuit 441 has adiode D1 connected between the low pass filter 431 and the branchingfilter 460 and a λ/4 transmission line TL1 and a diode D2 connected inseries between the cathode terminal of the diode D1 and the groundpoint.

In the transmission/reception switching circuit 441, at the time oftransmission, the diode D1 is turned on and a transmission signal fromthe power amplifier side is transmitted to the branching filter 460. Atthis time, the diode D2 is also turned on, the other end of the λ/4transmission line TL1 is short-circuit to the ground potential, and theimpedance seen from the diode D1 side to the λ/4 transmission line TL1becomes high. Consequently, while preventing leakage of the signal tothe reception side, the signal can be transmitted to the antenna ANT. Onthe other hand, at the time of reception, both of the two diodes D1 andD2 are turned off. Therefore, a reception signal from the antenna ANT istransmitted to the SAW filter 120A side in FIG. 1 via the branchingfilter 460, λ/4 transmission line TL1, and capacitor C21. Thetransmission/reception switching circuit 442 on the GSM side has asimilar configuration, so that it will not be described.

In the case where the front end module 400 is constructed as shown inFIG. 9, the transmission/reception switching circuits 441 and 442 switchtransmission/reception signals by the diodes D1 and D2, so that thesignal transmission path from the power amplifier 210 b to the antennaANT cannot be completely interrupted. Since the DCS signal has afrequency about twice as high as that of the GSM signal, when harmonicstwice as high as the GSM signal are transmitted from the power amplifier210 a on the GSM side to the power amplifier 210 b on the DCS side, theharmonics cannot be blocked by the low pass filter 431. Consequently, itis feared that a leaked signal from the power amplifier 410 b on the DCSside is added as a noise to a signal which is output from the poweramplifier 410 a on the GSM side to the antenna ANT in the GSM mode.

Therefore, as in the embodiment of FIG. 7, by providing the outputterminal Pout-DCS of the power amplifier 210 b on the DCS side with thestate switching circuit 240, in the GSM mode, a leaked signal from thepower amplifier 210 b on the DCS side can be prevented from being addedas a noise to a GSM transmission signal.

FIG. 8 shows a schematic configuration of a third embodiment of the RFpower module 200 to which the invention is applied.

In the RF power module 200 of the embodiment, a time constant circuit233 functioning as a filter is provided between an input terminal towhich a signal from the output detection circuit 220 is input and anoutput terminal of the comparing circuit 231, and external terminals P1and P2 are provided for the module so that a resistive element and acapacitative element provided in parallel and constructing the timeconstant circuit 233 can be connected as external parts.

The output level instruction signal Vramp from the CPU 500, which isinput to the other input terminal of the comparing circuit 231 is asignal having a stepped waveform which is output from a D/A converter inthe CPU, and an output of the comparing circuit 231 also has a steppedwaveform. The time constant circuit 233 acts to smooth the signal havingthe stepped waveform. By constructing the elements (resistive andcapacitive elements) constructing the time constant circuit 233 so as tobe connected as external elements, there is an advantage such that theuser can arbitrarily set a time constant in accordance with a systemdesigned by himself/herself and the characteristics of the system can beimproved.

Although the invention achieved by the inventors herein has beenconcretely described above on the basis of the embodiments, obviously,the invention is not limited to the foregoing embodiments but can bevariously modified without departing from the gist. For example, in theembodiments, the RF power module and the front end module areconstructed as separate modules, they may be constructed as a singlemodule.

In the RF power amplifier of the embodiments, the power amplificationFETs are connected in three stages. The power amplification FETs can bealso connected in two stages or four or more stages. Each of the FETs212 and 213 in the second and third stages may be constructed by twoFETs connected in parallel. Further, each of the power amplification FETin the first stage and the current-mirror FET may take the form of adual-gate FET and a voltage obtained by dividing the bias current Ic1from the bias control circuit 232 by a resistor is applied to each ofthe gates to pass a desired drain current.

Further, in the embodiments, it has been described that the RF powermodule is constructed by the semiconductor integrated circuit includingthe first and second amplification stages 211 and 212 and the outputpower control circuit 230, the semiconductor integrated circuitincluding the FET 31 and the current mirror FET 32 in the third stageand the FET 221 for output detection, and external elements such asresistive and capacitative elements. Alternately, the two semiconductorintegrated circuits may be constructed as a single semiconductorintegrated circuit.

Industrial Applicability

Although the case where the invention is applied to the dual-band RFpower amplifier capable of performing communications in the GSM and DCSmodes has been described in the embodiments, the invention can be alsoapplied to an RF power amplifier as a component of a triple-bandcommunication system capable of performing communications not only inthe GSM and DCS modes but also in a PCS (Personal Communications System)mode using a frequency band of 1900 MHz. In this case, DCS and PCSsignals may be amplified by a common power amplifier or separate poweramplifiers.

1-17. (canceled)
 18. A High frequency power module, comprising: a firstamplification means for amplifying a first modulated signal to betransmit; a second amplification means for amplifying a second modulatedsignal to be transmit which is different from the first modulatedsignal; a power detection means for generating a voltage related to anoutput power of the first amplification means or an output power thesecond amplification means; and a bias means for supplying bias signalsin accordance with the voltage and an output power instruction signal;wherein the power detection means including a first detector whichgenerates a first signal in connection with the passing current of thefirst amplification means, a second detector which generates a secondsignal in connection with the passing current of the secondamplification means and a sense resistor which receives the first signaland the second signal and generates the voltage, wherein the firstdetector includes a first detection transistor and a first currentmirror circuit which couples the first detection transistor and suppliesthe first signal to the sense resistor; and wherein the second detectorincludes a second detection transistor and a second current mirrorcircuit which couples the second detection transistor and supplies thesecond signal to the sense resistor.
 19. A High frequency power moduleaccording to claim 18, wherein when an output level of the firstmodulation signal and that of the second modulation signal are differentfrom each other, a ratio between current in a transfer source of thefirst current mirror circuit and the second current mirror circuit andcurrent on the transfer side of the first current mirror circuit and thesecond current mirror circuit is set so that magnitudes of currentsflowing in the sense resistor become almost equal to each other in thecase where either the first amplification means or the secondamplification means operates at a maximum output level.
 20. A Highfrequency power module according to claim 18, wherein the bias meanscomprising a comparing circuit for comparing the voltage with the outputpower instruction signal.
 21. A High frequency power module according toclaim 19, wherein the first amplification means comprising a pluralityof amplifying stages which is connected in series and each of theplurality of amplifying stages has an amplification transistor and abias transistor which forms a current mirror circuit, wherein the secondamplification means comprising a plurality of amplifying stages which isconnected in series and each of the plurality of amplifying stages hasan amplification transistor and a bias transistor which forms a currentmirror circuit, wherein the bias signals are supplied to each of theplurality of amplifying stages of the first amplification means and thesecond amplification means by passing a predetermined control currentfrom the bias means to the bias transistors.
 22. A High frequency powermodule according to claim 21, wherein the first detection transistorreceives an signal to be input to the final stage of the firstamplification means, wherein the second detection transistor receives ansignal to be input to the final stage of the second amplification means.23. A High frequency power module according to claim 22, wherein thefirst modulated signal is a GSM transmission signal and the secondmodulated signal is a DCS transmission signal.
 24. A High frequencypower module according to claim 23, further comprising a switch meansfor switching the first amplification means and the second amplificationmeans, wherein the switch means is turned on when the firstamplification means is operated and is turned off when the secondamplification means is operated.
 25. A High frequency power moduleaccording to claim 24, wherein the switch means includes a MOSFET havinghigh breakdown voltage.